OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [vect/] [vect-strided-a-u32-mult.c] - Blame information for rev 705

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-require-effective-target vect_int } */
2
 
3
#include <stdarg.h>
4
#include "tree-vect.h"
5
 
6
#define N 128
7
 
8
typedef struct {
9
   unsigned int a;
10
   unsigned int b;
11
} ii;
12
 
13
__attribute__ ((noinline)) int
14
main1 ()
15
{
16
  unsigned short arr[N];
17
  unsigned short *ptr = arr;
18
  ii iarr[N];
19
  ii *iptr = iarr;
20
  unsigned short res[N];
21
  ii ires[N];
22
  int i;
23
 
24
  for (i = 0; i < N; i++)
25
    {
26
      arr[i] = i;
27
      iarr[i].a = i;
28
      iarr[i].b = i * 3;
29
      __asm__ volatile ("");
30
    }
31
 
32
  for (i = 0; i < N; i++)
33
    {
34
      ires[i].a = iptr->b - iptr->a;
35
      ires[i].b = iptr->b + iptr->a;
36
      res[i] = *ptr;
37
      iptr++;
38
      ptr++;
39
    }
40
 
41
  /* check results:  */
42
  for (i = 0; i < N; i++)
43
    {
44
      if (res[i] != arr[i]
45
          || ires[i].a != iarr[i].b - iarr[i].a
46
          || ires[i].b != iarr[i].b +  iarr[i].a)
47
        abort ();
48
    }
49
 
50
  return 0;
51
}
52
 
53
int main (void)
54
{
55
  int i;
56
 
57
  check_vect ();
58
 
59
  main1 ();
60
 
61
  return 0;
62
}
63
 
64
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { target vect_strided2 } } } */
65
/* { dg-final { cleanup-tree-dump "vect" } } */
66
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.