OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.dg/] [vect/] [vect-strided-store-u32-i2.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 689 jeremybenn
/* { dg-require-effective-target vect_int } */
2
 
3
#include <stdarg.h>
4
#include "tree-vect.h"
5
 
6
#define N 16
7
 
8
int a[N*2];
9
int b[N] = {0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30};
10
int c[N] = {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31};
11
 
12
__attribute__ ((noinline)) int
13
main1 (void)
14
{
15
  int i;
16
 
17
  /* Strided access pattern.  */
18
  for (i = 0; i < N/2; i++)
19
    {
20
      a[i*2] = b[i] + c[i];
21
      a[i*2+1] = b[i] * c[i];
22
    }
23
 
24
  /* Check results.  */
25
  for (i = 0; i < N/2; i++)
26
    {
27
      if (a[i*2] != b[i] + c[i]
28
          || a[i*2+1] != b[i] * c[i])
29
        abort();
30
    }
31
 
32
  return 0;
33
}
34
 
35
int main (void)
36
{
37
  check_vect ();
38
  return main1 ();
39
}
40
 
41
/* Needs interleaving support.  */
42
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_interleave || vect_strided2 } } } } */
43
/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { vect_interleave || vect_strided2 } } } } */
44
/* { dg-final { cleanup-tree-dump "vect" } } */
45
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.