OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.misc-tests/] [i386-pf-sse-1.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 690 jeremybenn
/* Test that the correct data prefetch instructions are generated for i386
2
   variants that use SSE prefetch instructions.  */
3
 
4
/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
5
 
6
extern void exit (int);
7
 
8
char *msg = "howdy there";
9
 
10
void foo (char *p)
11
{
12
  __builtin_prefetch (p, 0, 0);
13
  __builtin_prefetch (p, 0, 1);
14
  __builtin_prefetch (p, 0, 2);
15
  __builtin_prefetch (p, 0, 3);
16
  __builtin_prefetch (p, 1, 0);
17
  __builtin_prefetch (p, 1, 1);
18
  __builtin_prefetch (p, 1, 2);
19
  __builtin_prefetch (p, 1, 3);
20
}
21
 
22
int main ()
23
{
24
  foo (msg);
25
  exit (0);
26
}
27
 
28
/* { dg-final { scan-assembler "prefetchnta" } } */
29
/* { dg-final { scan-assembler "prefetcht0" } } */
30
/* { dg-final { scan-assembler "prefetcht1" } } */
31
/* { dg-final { scan-assembler "prefetcht2" } } */
32
/* { dg-final { scan-assembler-not "prefetchw" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.