OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [20090811-1.c] - Blame information for rev 751

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
3
/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-a8" } } */
4
/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
5
/* { dg-options "-O3 -mcpu=cortex-a8 -mfpu=vfp3 -mfloat-abi=softfp" } */
6
 
7
typedef struct cb
8
{
9
  int cxc;
10
  short int pside;
11
}  *CBPTR;
12
typedef struct rwb
13
{
14
  int stx;
15
} RWB;
16
extern CBPTR *car;
17
extern RWB *rwAr;
18
extern int nts;
19
extern int nRws;
20
void f()
21
{
22
  CBPTR pptr ;
23
  int  k_lt, k_rt, k_span, rw, p, rt;
24
  int sa ;
25
  k_rt = 0;
26
  k_lt = 10000000;
27
  for (rw = 1; rw <= nRws; rw++)
28
    k_lt = rwAr[rw].stx;
29
  k_span = k_rt - k_lt;
30
  for (; p <= nts; p++)
31
    {
32
      pptr = car[p];
33
      if (pptr->pside == 3)
34
        pptr->cxc += (int)(((double)rt / (double) k_span) *((double) sa));
35
    }
36
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.