OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vRhaddQu32.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
2
/* This file was autogenerated by neon-testgen.  */
3
 
4
/* { dg-do assemble } */
5
/* { dg-require-effective-target arm_neon_ok } */
6
/* { dg-options "-save-temps -O0" } */
7
/* { dg-add-options arm_neon } */
8
 
9
#include "arm_neon.h"
10
 
11
void test_vRhaddQu32 (void)
12
{
13
  uint32x4_t out_uint32x4_t;
14
  uint32x4_t arg0_uint32x4_t;
15
  uint32x4_t arg1_uint32x4_t;
16
 
17
  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
18
}
19
 
20
/* { dg-final { scan-assembler "vrhadd\.u32\[   \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[         \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
21
/* { dg-final { cleanup-saved-temps } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.