OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon-cond-1.c] - Blame information for rev 764

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target arm_neon_hw } */
3
/* { dg-options "-O2" } */
4
/* { dg-add-options arm_neon } */
5
/* Check that the arm_final_prescan_insn ccfsm code does not try to
6
 * conditionally execute NEON instructions.  */
7
#include <arm_neon.h>
8
#include <stdlib.h>
9
 
10
int __attribute__((noinline))
11
foo(uint32x2_t a, uint32_t *p, uint32_t *q)
12
{
13
  if (p != q)
14
    /* This vst1 instruction could be conditional, except that NEON
15
       instructions are never conditional in ARM mode.  */
16
    vst1_u32(p, a);
17
  return 0;
18
}
19
 
20
int
21
main()
22
{
23
    uint32x2_t v;
24
    uint32_t a[2] = {1, 42};
25
    v = vld1_u32(a);
26
    v = vadd_u32(v, v);
27
    foo(v, a, a);
28
    if (a[0] != 1 || a[1] != 42)
29
      abort();
30
    exit(0);
31
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.