OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon-vshl-imm-1.c] - Blame information for rev 708

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-require-effective-target arm_neon_ok } */
3
/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
4
/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */
5
 
6
/* Verify that VSHR immediate is used.  */
7
void f1(int n, int x[], int y[]) {
8
  int i;
9
  for (i = 0; i < n; ++i)
10
    y[i] = x[i] << 3;
11
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.