OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [pr40657-2.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-options "-Os -mthumb" }  */
2
/* { dg-require-effective-target arm_thumb1_ok } */
3
/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */
4
/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */
5
 
6
/* Here, we test that if there's a pop of r[4567] in the epilogue,
7
   add sp,sp,#12 is removed and replaced by three additional pops
8
   of lower-numbered regs.  */
9
 
10
extern void bar(int*);
11
 
12
int t1, t2, t3, t4, t5;
13
int foo()
14
{
15
  int i,j,k,x = 0;
16
  for (i = 0; i < t1; i++)
17
    for (j = 0; j < t2; j++)
18
          bar(&x);
19
  return x;
20
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.