OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [pr48183.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* testsuite/gcc.target/arm/pr48183.c */
2
 
3
/* { dg-do compile } */
4
/* { dg-require-effective-target arm_neon_ok } */
5
/* { dg-options "-O -g" } */
6
/* { dg-add-options arm_neon } */
7
 
8
#include <arm_neon.h>
9
 
10
void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n)
11
{
12
    unsigned i;
13
    int16x4x2_t input;
14
    int32x4x2_t mid;
15
    int32x4x2_t output;
16
 
17
    for (i = 0; i < n/2; i += 8) {
18
        input = vld2_s16(src + i);
19
        mid.val[0] = vmovl_s16(input.val[0]);
20
        mid.val[1] = vmovl_s16(input.val[1]);
21
        output.val[0] = vshlq_n_s32(mid.val[0], 8);
22
        output.val[1] = vshlq_n_s32(mid.val[1], 8);
23
        vst2q_s32((int32_t *)dst + i, output);
24
    }
25
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.