OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [pr48252.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target arm_neon_hw } */
3
/* { dg-options "-O2" } */
4
/* { dg-add-options arm_neon } */
5
 
6
#include "arm_neon.h"
7
#include <stdlib.h>
8
 
9
int main(void)
10
{
11
    uint8x8_t v1 = {1, 1, 1, 1, 1, 1, 1, 1};
12
    uint8x8_t v2 = {2, 2, 2, 2, 2, 2, 2, 2};
13
    uint8x8x2_t vd1, vd2;
14
    union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4;
15
    int i;
16
 
17
    vd1 = vzip_u8(v1, vdup_n_u8(0));
18
    vd2 = vzip_u8(v2, vdup_n_u8(0));
19
 
20
    vst1_u8(d1.buf, vd1.val[0]);
21
    vst1_u8(d2.buf, vd1.val[1]);
22
    vst1_u8(d3.buf, vd2.val[0]);
23
    vst1_u8(d4.buf, vd2.val[1]);
24
 
25
    for (i = 0; i < 8; i++)
26
      if ((i % 2 == 0 && d4.buf[i] != 2)
27
          || (i % 2 == 1 && d4.buf[i] != 0))
28
         abort ();
29
 
30
    return 0;
31
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.