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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [pr50305.c] - Blame information for rev 691

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Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
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/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
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/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3" } */
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struct event {
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 unsigned long long id;
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 unsigned int flag;
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};
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void dummy(void)
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{
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  /* This is here to ensure that the offset of perf_event_id below
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     relative to the LANCHOR symbol exceeds the allowed displacement.  */
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  static int __warned[300];
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 __warned[0] = 1;
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}
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extern void *kmem_cache_alloc_trace (void *cachep);
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extern void *cs_cachep;
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extern int nr_cpu_ids;
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struct event *
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event_alloc (int cpu)
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{
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 static unsigned long long __attribute__((aligned(8))) perf_event_id;
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 struct event *event;
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 unsigned long long result;
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 unsigned long tmp;
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 if (cpu >= nr_cpu_ids)
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  return 0;
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 event = kmem_cache_alloc_trace (cs_cachep);
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 __asm__ __volatile__ ("dmb" : : : "memory");
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 __asm__ __volatile__("@ atomic64_add_return\n"
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"1:     ldrexd  %0, %H0, [%3]\n"
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"       adds    %0, %0, %4\n"
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"       adc     %H0, %H0, %H4\n"
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"       strexd  %1, %0, %H0, [%3]\n"
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"       teq     %1, #0\n"
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"       bne     1b"
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 : "=&r" (result), "=&r" (tmp), "+Qo" (perf_event_id)
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 : "r" (&perf_event_id), "r" (1LL)
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 : "cc");
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 __asm__ __volatile__ ("dmb" : : : "memory");
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 event->id = result;
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 if (cpu)
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  event->flag = 1;
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 for (cpu = 0; cpu < nr_cpu_ids; cpu++)
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   kmem_cache_alloc_trace (cs_cachep);
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 return event;
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}
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