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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [shiftable.c] - Blame information for rev 801

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Line No. Rev Author Line
1 691 jeremybenn 
/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-require-effective-target arm32 } */
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/* ARM has shift-and-alu insns.  Depending on the ALU op GCC represents some
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   of these as a left shift, others as a multiply.  Check that we match the
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    right one.  */
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int
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plus (int a, int b)
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{
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  return (a * 64) + b;
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}
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/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */
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int
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minus (int a, int b)
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{
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  return a - (b * 64);
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}
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/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */
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int
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ior (int a, int b)
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{
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  return (a * 64) | b;
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}
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/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */
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int
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xor (int a, int b)
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{
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  return (a * 64) ^ b;
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}
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/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */
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int
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and (int a, int b)
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{
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  return (a * 64) & b;
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}
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/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */
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int
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rsb (int a, int b)
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{
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  return (a * 64) - b;
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}
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/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */
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int
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mvn (int a, int b)
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{
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  return ~(a * 64);
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}
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/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */

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