OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [thumb-cbranchqi.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-mthumb -Os" }  */
3
/* { dg-require-effective-target arm_thumb1_ok } */
4
 
5
int ldrb(unsigned char* p)
6
{
7
  if (p[8] <= 0x7F)
8
    return 2;
9
  else
10
    return 5;
11
}
12
 
13
 
14
/* { dg-final { scan-assembler "127" } } */
15
/* { dg-final { scan-assembler "bhi" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.