OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [wmul-bitfield-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2" } */
3
/* { dg-require-effective-target arm_dsp } */
4
 
5
struct bf
6
{
7
  int a : 3;
8
  int b : 15;
9
  int c : 3;
10
};
11
 
12
long long
13
foo (long long a, struct bf b, struct bf c)
14
{
15
  return a + b.b * c.b;
16
}
17
 
18
/* { dg-final { scan-assembler "smlalbb" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.