OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [avx2-vpblendd256-2.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-mavx2 -O2" } */
3
/* { dg-require-effective-target avx2 } */
4
 
5
#include "avx2-check.h"
6
#include <string.h>
7
 
8
#define NUM 20
9
 
10
#undef MASK
11
#define MASK 0xf1
12
 
13
static void
14
init_pblendd256 (int *src1, int *src2, int seed)
15
{
16
  int i, sign = 1;
17
 
18
  for (i = 0; i < 8; i++)
19
    {
20
      src1[i] = (i + seed) * (i + seed) * sign;
21
      src2[i] = (i + seed + 20) * sign;
22
      sign = -sign;
23
    }
24
}
25
 
26
static void
27
calc_pblendd256 (int *src1, int *src2, unsigned int mask, int *dst)
28
{
29
  int i;
30
 
31
  memcpy (dst, src1, 32);
32
  for (i = 0; i < 8; i++)
33
    if (mask & (1 << i))
34
      dst[i] = src2[i];
35
}
36
 
37
static void
38
avx2_test (void)
39
{
40
  union256i_d src1, src2, dst;
41
  int dst_ref[8];
42
  int i;
43
 
44
  for (i = 0; i < NUM; i++)
45
    {
46
      init_pblendd256 (src1.a, src2.a, i);
47
 
48
      dst.x = _mm256_blend_epi32 (src1.x, src2.x, MASK);
49
      calc_pblendd256 (src1.a, src2.a, MASK, dst_ref);
50
 
51
      if (check_union256i_d (dst, dst_ref))
52
        abort ();
53
    }
54
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.