OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [divmod-7.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile { target { ! { ia32 } } } } */
2
/* { dg-options "-O2 -m8bit-idiv" } */
3
 
4
extern void abort (void);
5
 
6
void
7
test (long long x, long long y, long long q, long long r)
8
{
9
  if ((x / y) != q || (x % y) != r)
10
    abort ();
11
}
12
 
13
/* { dg-final { scan-assembler-times "divb" 1 } } */
14
/* { dg-final { scan-assembler-times "idivq" 1 } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.