URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [movq.c] - Blame information for rev 691

Details | Compare with Previous | View Log


/* { dg-do compile }
/* { dg-options "-Os -march=pentium4 -mtune=prescott" } */
/* { dg-require-effective-target ia32 } */
 
register char foo asm("edi");
char x;
int bar() {
  foo = x;
}
/* { dg-final { scan-assembler "movz" } } */

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* { dg-do compile }`
2			`/* { dg-options "-Os -march=pentium4 -mtune=prescott" } */`
3			`/* { dg-require-effective-target ia32 } */`
4
5			`register char foo asm("edi");`
6			`char x;`
7			`int bar() {`
8			`foo = x;`
9			`}`
10			`/* { dg-final { scan-assembler "movz" } } */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [movq.c] - Blame information for rev 691