OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr27266.c] - Blame information for rev 695

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* PR target/27266.
2
   The testcase below used to trigger an ICE.  */
3
 
4
/* { dg-do compile } */
5
/* { dg-require-effective-target ia32 } */
6
/* { dg-options "-march=pentium" } */
7
 
8
signed long long sll;
9
 
10
void
11
foo (void)
12
{
13
  __sync_fetch_and_add (&sll, 1);
14
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.