OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr28946.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-Os" } */
3
/* { dg-final { scan-assembler-not "test" } } */
4
 
5
int fct1 (void);
6
int fct2 (void);
7
 
8
int
9
fct (unsigned nb)
10
{
11
  if ((nb >> 5) != 0)
12
    return fct1 ();
13
  else
14
    return fct2 ();
15
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.