OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr38824.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2 -msse -mno-sse2" } */
3
 
4
typedef float v4sf __attribute__ ((__vector_size__ (16)));
5
 
6
void bench_1(float * out, float * in, float f, unsigned int n)
7
{
8
    n /= 4;
9
    v4sf scalar = { f, f, f, f };
10
    do
11
    {
12
        v4sf arg = *(v4sf *)in;
13
        v4sf result = arg + scalar;
14
        *(v4sf *) out = result;
15
        in += 4;
16
        out += 4;
17
    }
18
    while (--n);
19
}
20
 
21
/* { dg-final { scan-assembler-not "addps\[^\\n\]*%\[er\]" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.