OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr39911.c] - Blame information for rev 700

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do assemble } */
2
/* { dg-options "-O2" } */
3
 
4
void
5
bar1 ()
6
{
7
  char foo;
8
  asm volatile ("mov%z0 %1, %0": "=m" (foo): "iq" (-23));
9
  asm volatile ("add%z0 %1, %0": "+m" (foo): "iq" (23));
10
  asm volatile ("mov%z0 %1, %0": "=q" (foo): "iq" (-23));
11
  asm volatile ("add%z0 %1, %0": "+q" (foo): "iq" (23));
12
}
13
 
14
void
15
bar2 ()
16
{
17
  short foo;
18
  asm volatile ("mov%z0 %1, %0": "=m" (foo): "ir" (-23));
19
  asm volatile ("add%z0 %1, %0": "+m" (foo): "ir" (23));
20
  asm volatile ("mov%z0 %1, %0": "=r" (foo): "ir" (-23));
21
  asm volatile ("add%z0 %1, %0": "+r" (foo): "ir" (23));
22
 
23
  asm volatile ("pop%z0 %0": "=m" (foo));
24
  asm volatile ("pop%z0 %0": "=r" (foo));
25
}
26
 
27
void
28
bar3 ()
29
{
30
  int foo;
31
  asm volatile ("mov%z0 %1, %0": "=m" (foo): "ir" (-23));
32
  asm volatile ("add%z0 %1, %0": "+m" (foo): "ir" (23));
33
  asm volatile ("mov%z0 %1, %0": "=r" (foo): "ir" (-23));
34
  asm volatile ("add%z0 %1, %0": "+r" (foo): "ir" (23));
35
 
36
#ifndef __x86_64__
37
  if (sizeof (void *) == sizeof (int))
38
    {
39
      asm volatile ("pop%z0 %0": "=m" (foo));
40
      asm volatile ("pop%z0 %0": "=r" (foo));
41
    }
42
#endif
43
}
44
 
45
void
46
bar4 ()
47
{
48
  if (sizeof (void *) == sizeof (long long))
49
    {
50
      long long foo;
51
      asm volatile ("mov%z0 %1, %0": "=m" (foo): "er" (-23));
52
      asm volatile ("add%z0 %1, %0": "+m" (foo): "er" (23));
53
      asm volatile ("mov%z0 %1, %0": "=r" (foo): "er" (-23));
54
      asm volatile ("add%z0 %1, %0": "+r" (foo): "er" (23));
55
 
56
      asm volatile ("pop%z0 %0": "=m" (foo));
57
      asm volatile ("pop%z0 %0": "=r" (foo));
58
    }
59
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.