OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse-15.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2 -msse -msse2" } */
3
 
4
/* Test that the intrinsics compile with optimization.  These were not
5
   tested in i386-sse-[12].c because these builtins require immediate
6
   operands.  */
7
 
8
#include <xmmintrin.h>
9
 
10
__m128
11
test_shuf (void)
12
{
13
  __m128 a = _mm_set1_ps (1.0);
14
  __m128 b = _mm_set1_ps (2.0);
15
  return _mm_shuffle_ps (a, b, _MM_SHUFFLE (0,1,2,3));
16
}
17
 
18
__m64
19
test_ins_ext (__m64 a)
20
{
21
  return _mm_insert_pi16 (a, _mm_extract_pi16 (a, 0), 3);
22
}
23
 
24
__m64
25
test_shuf2 (__m64 a)
26
{
27
  return _mm_shuffle_pi16 (a, 0xA5);
28
}
29
 
30
void
31
test_prefetch (char *p)
32
{
33
  _mm_prefetch (p, _MM_HINT_T0);
34
  _mm_prefetch (p+4, _MM_HINT_T1);
35
  _mm_prefetch (p+8, _MM_HINT_T2);
36
  _mm_prefetch (p+12, _MM_HINT_NTA);
37
}
38
 
39
__m128i
40
test__slli_si128 (__m128i a)
41
{
42
  return _mm_slli_si128 (a, 3);
43
}
44
 
45
__m128i
46
test__srli_si128 (__m128i a)
47
{
48
  return _mm_srli_si128 (a, 3);
49
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.