OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse2-pmaxub-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-O2 -msse2" } */
3
/* { dg-require-effective-target sse2 } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "sse2-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST sse2_test
11
#endif
12
 
13
#include CHECK_H
14
 
15
#include <emmintrin.h>
16
 
17
static __m128i
18
__attribute__((noinline, unused))
19
test (__m128i s1, __m128i s2)
20
{
21
  return _mm_max_epu8 (s1, s2);
22
}
23
 
24
static void
25
TEST (void)
26
{
27
  union128i_ub u, s1, s2;
28
  unsigned char e[16];
29
  int i;
30
 
31
  s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);
32
  s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1);
33
  u.x = test (s1.x, s2.x);
34
 
35
  for (i=0; i<16; i++)
36
    e[i] = s1.a[i]>s2.a[i]?s1.a[i]:s2.a[i];
37
 
38
  if (check_union128i_ub (u, e))
39
    abort ();
40
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.