OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse4_1-cond-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target sse4 } */
3
/* { dg-options "-O3 -msse4.1" } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "sse4_1-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST sse4_1_test
11
#endif
12
 
13
#include CHECK_H
14
 
15
extern void abort (void);
16
double ad[64], bd[64], cd[64], dd[64], ed[64];
17
float af[64], bf[64], cf[64], df[64], ef[64];
18
signed char ac[64], bc[64], cc[64], dc[64], ec[64];
19
short as[64], bs[64], cs[64], ds[64], es[64];
20
int ai[64], bi[64], ci[64], di[64], ei[64];
21
long long all[64], bll[64], cll[64], dll[64], ell[64];
22
unsigned char auc[64], buc[64], cuc[64], duc[64], euc[64];
23
unsigned short aus[64], bus[64], cus[64], dus[64], eus[64];
24
unsigned int au[64], bu[64], cu[64], du[64], eu[64];
25
unsigned long long aull[64], bull[64], cull[64], dull[64], eull[64];
26
 
27
#define F(var) \
28
__attribute__((noinline, noclone)) void \
29
f##var (void) \
30
{ \
31
  int i; \
32
  for (i = 0; i < 64; i++) \
33
    { \
34
      __typeof (a##var[0]) d = d##var[i], e = e##var[i]; \
35
      a##var[i] = b##var[i] > c##var[i] ? d : e; \
36
    } \
37
}
38
 
39
#define TESTS \
40
F (d) F (f) F (c) F (s) F (i) F (ll) F (uc) F (us) F (u) F (ull)
41
 
42
TESTS
43
 
44
void
45
TEST ()
46
{
47
  int i;
48
  for (i = 0; i < 64; i++)
49
    {
50
#undef F
51
#define F(var) \
52
      b##var[i] = i + 64; \
53
      switch (i % 3) \
54
        { \
55
        case 0: c##var[i] = i + 64; break; \
56
        case 1: c##var[i] = 127 - i; break; \
57
        case 2: c##var[i] = i; break; \
58
        } \
59
      d##var[i] = i / 2; \
60
      e##var[i] = i * 2;
61
      TESTS
62
    }
63
#undef F
64
#define F(var) f##var ();
65
  TESTS
66
  for (i = 0; i < 64; i++)
67
    {
68
      asm volatile ("" : : : "memory");
69
#undef F
70
#define F(var) \
71
      if (a##var[i] != (b##var[i] > c##var[i] ? d##var[i] : e##var[i])) \
72
        abort ();
73
      TESTS
74
    }
75
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.