OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse4_1-pmovzxdq.c] - Blame information for rev 724

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target sse4 } */
3
/* { dg-options "-O2 -msse4.1" } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "sse4_1-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST sse4_1_test
11
#endif
12
 
13
#include CHECK_H
14
 
15
#include <smmintrin.h>
16
 
17
#define NUM 128
18
 
19
static void
20
TEST (void)
21
{
22
  union
23
    {
24
      __m128i x[NUM / 2];
25
      unsigned long long ll[NUM];
26
      unsigned int i[NUM * 2];
27
    } dst, src;
28
  int i;
29
 
30
  for (i = 0; i < NUM; i++)
31
    {
32
      src.i[(i % 2) + (i / 2) * 4] = i * i;
33
      if ((i % 2))
34
        src.i[(i % 2) + (i / 2) * 4] |= 0x80000000;
35
    }
36
 
37
  for (i = 0; i < NUM; i += 2)
38
    dst.x [i / 2] = _mm_cvtepu32_epi64 (src.x [i / 2]);
39
 
40
  for (i = 0; i < NUM; i++)
41
    if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
42
      abort ();
43
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.