OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [testimm-7.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* PR target/49411 */
2
/* { dg-do assemble } */
3
/* { dg-options "-O0 -mxop" } */
4
/* { dg-require-effective-target xop } */
5
 
6
#include <x86intrin.h>
7
 
8
__m128i i1, i2, i3, i4;
9
__m128 a1, a2, a3, a4;
10
__m128d d1, d2, d3, d4;
11
__m256i l1, l2, l3, l4;
12
__m256 b1, b2, b3, b4;
13
__m256d e1, e2, e3, e4;
14
__m64 m1, m2, m3, m4;
15
int k1, k2, k3, k4;
16
float f1, f2, f3, f4;
17
 
18
void
19
test2bit (void)
20
{
21
  d1 = _mm_permute2_pd (d2, d3, i1, 3);
22
  e1 = _mm256_permute2_pd (e2, e3, l1, 3);
23
  a1 = _mm_permute2_ps (a2, a3, i1, 3);
24
  b1 = _mm256_permute2_ps (b2, b3, l1, 3);
25
  d1 = _mm_permute2_pd (d2, d3, i1, 0);
26
  e1 = _mm256_permute2_pd (e2, e3, l1, 0);
27
  a1 = _mm_permute2_ps (a2, a3, i1, 0);
28
  b1 = _mm256_permute2_ps (b2, b3, l1, 0);
29
}
30
 
31
void
32
test2args (void)
33
{
34
  i1 = _mm_extracti_si64 (i2, 255, 0);
35
  i1 = _mm_extracti_si64 (i2, 0, 255);
36
  i1 = _mm_inserti_si64 (i2, i3, 255, 0);
37
  i2 = _mm_inserti_si64 (i2, i3, 0, 255);
38
  i1 = _mm_extracti_si64 (i2, 255, 255);
39
  i1 = _mm_extracti_si64 (i2, 255, 255);
40
  i1 = _mm_inserti_si64 (i2, i3, 255, 255);
41
  i2 = _mm_inserti_si64 (i2, i3, 255, 255);
42
  i1 = _mm_extracti_si64 (i2, 0, 0);
43
  i1 = _mm_extracti_si64 (i2, 0, 0);
44
  i1 = _mm_inserti_si64 (i2, i3, 0, 0);
45
  i2 = _mm_inserti_si64 (i2, i3, 0, 0);
46
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.