OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [vperm-v4si-2.c] - Blame information for rev 695

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target ssse3 } */
3
/* { dg-options "-O -mssse3" } */
4
 
5
#include "isa-check.h"
6
 
7
typedef int S;
8
typedef int V __attribute__((vector_size(16)));
9
typedef int IV __attribute__((vector_size(16)));
10
typedef union { S s[4]; V v; } U;
11
 
12
static U i[2], b, c;
13
 
14
extern int memcmp (const void *, const void *, __SIZE_TYPE__);
15
#define assert(T) ((T) || (__builtin_trap (), 0))
16
 
17
#define TEST(E0, E1, E2, E3) \
18
  b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \
19
  c.s[0] = i[0].s[E0]; \
20
  c.s[1] = i[0].s[E1]; \
21
  c.s[2] = i[0].s[E2]; \
22
  c.s[3] = i[0].s[E3]; \
23
  __asm__("" : : : "memory"); \
24
  assert (memcmp (&b, &c, sizeof(c)) == 0);
25
 
26
#include "vperm-4-2.inc"
27
 
28
int main()
29
{
30
  check_isa ();
31
 
32
  i[0].s[0] = 0;
33
  i[0].s[1] = 1;
34
  i[0].s[2] = 2;
35
  i[0].s[3] = 3;
36
  i[0].s[4] = 4;
37
  i[0].s[5] = 5;
38
  i[0].s[6] = 6;
39
  i[0].s[7] = 7;
40
 
41
  check();
42
  return 0;
43
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.