URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [xop-shift2-vector.c] - Blame information for rev 695

Go to most recent revision | Details | Compare with Previous | View Log


/* Test that the compiler properly optimizes vector shift instructions into
   psha/pshl on XOP systems.  */
 
/* { dg-do compile { target { ! { ia32 } } } } */
/* { dg-options "-O2 -mxop -ftree-vectorize" } */
 
extern void exit (int);
 
typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
 
#define SIZE 10240
 
union {
  __m128i i_align;
  int i32[SIZE];
  unsigned u32[SIZE];
} a, b, c;
 
void
right_sign_shift32 (void)
{
  int i;
 
  for (i = 0; i < SIZE; i++)
    a.i32[i] = b.i32[i] >> c.i32[i];
}
 
int main ()
{
  right_sign_shfit32 ();
  exit (0);
}
 
/* { dg-final { scan-assembler "vpshad" } } */

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* Test that the compiler properly optimizes vector shift instructions into`
2			`psha/pshl on XOP systems. */`
3
4			`/* { dg-do compile { target { ! { ia32 } } } } */`
5			`/* { dg-options "-O2 -mxop -ftree-vectorize" } */`
6
7			`extern void exit (int);`
8
9			`typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));`
10
11			`#define SIZE 10240`
12
13			`union {`
14			`__m128i i_align;`
15			`int i32[SIZE];`
16			`unsigned u32[SIZE];`
17			`} a, b, c;`
18
19			`void`
20			`right_sign_shift32 (void)`
21			`{`
22			`int i;`
23
24			`for (i = 0; i < SIZE; i++)`
25			`a.i32[i] = b.i32[i] >> c.i32[i];`
26			`}`
27
28			`int main ()`
29			`{`
30			`right_sign_shfit32 ();`
31			`exit (0);`
32			`}`
33
34			`/* { dg-final { scan-assembler "vpshad" } } */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [xop-shift2-vector.c] - Blame information for rev 695