OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [ia64/] [20030225-2.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do run } */
2
/* { dg-options "-O3" } */
3
 
4
extern void abort (void);
5
extern void exit (int);
6
 
7
int __attribute__((noinline, const))
8
ret4 (float value)
9
{
10
  return 4;
11
}
12
 
13
int __attribute__((noinline, const))
14
ret0 (float value)
15
{
16
  return 0;
17
}
18
 
19
float __attribute__((noinline))
20
test (float x, float y)
21
{
22
  int clsx = ret4 (x);
23
  int clsy = ret0 (y);
24
 
25
  if (clsx == 0 || clsy == 0
26
      || (y < 0 && clsx == 1 && clsy == 1))
27
    return x - y;
28
 
29
  return x < y ? 0 : x - y;
30
}
31
 
32
float a = 0.0, b;
33
 
34
int main (void)
35
{
36
  unsigned long e;
37
  b = a / a;
38
  __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (e));
39
  e &= ~0x7e000UL;
40
  __asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (e) : "memory");
41
  a = test (0, b);
42
  __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (e));
43
  if (e & 0x2000)
44
    abort ();
45
  exit (0);
46
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.