OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [ia64/] [20030405-1.c] - Blame information for rev 697

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O2" } */
3
 
4
int
5
foo (int x, int y)
6
{
7
  if (y == 0)
8
    {
9
      register long r8 asm ("r8");
10
      register long r15 asm ("r15") = 1;
11
      long retval;
12
      __asm __volatile ("foo" : "=r" (r8), "=r" (r15) : "1" (r15));
13
      retval = r8;
14
      y = retval;
15
    }
16
 
17
  {
18
    register long r8 asm ("r8");
19
    register long r15 asm ("r15") = 2;
20
    long retval;
21
    register long _out1 asm ("out1") = x;
22
    register long _out0 asm ("out0") = y;
23
    __asm __volatile ("foo"
24
                      : "=r" (r8), "=r" (r15) , "=r" (_out0), "=r" (_out1)
25
                      : "1" (r15) , "2" (_out0), "3" (_out1));
26
    retval = r8;
27
    return retval;
28
  }
29
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.