OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [mips/] [branch-5.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-options "-mshared -mabi=n32" } */
2
/* { dg-final { scan-assembler "\taddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */
3
/* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */
4
/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
5
/* { dg-final { scan-assembler-not "\\\$28" } } */
6
 
7
#include "branch-helper.h"
8
 
9
NOMIPS16 void
10
foo (volatile int *x)
11
{
12
  if (__builtin_expect (*x == 0, 1))
13
    OCCUPY_0x1fffc;
14
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.