OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [mips/] [fpr-moves-2.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-options "-mabi=32 -mhard-float -mips1 -O2 -EB" } */
2
 
3
NOMIPS16 void
4
foo (double d, double *x)
5
{
6
  *x = d;
7
}
8
 
9
NOMIPS16 double
10
bar (double d)
11
{
12
  register double l1 asm ("$8") = d;
13
  register double l2 asm ("$f20") = 0.0;
14
  asm ("#foo" : "=d" (l1) : "d" (l1));
15
  asm volatile ("#foo" :: "f" (l2));
16
  return l1;
17
}
18
 
19
/* { dg-final { scan-assembler "\tswc1\t\\\$f12,4\\\(\\\$6\\\)\n" } } */
20
/* { dg-final { scan-assembler "\tswc1\t\\\$f13,0\\\(\\\$6\\\)\n" } } */
21
/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */
22
/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f13\n" } } */
23
/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
24
/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f21\n" } } */
25
/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */
26
/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f1\n" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.