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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [mips/] [loongson-shift-count-truncated-1.c] - Blame information for rev 696

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Line No. Rev Author Line
1 691 jeremybenn
/* Test case for SHIFT_COUNT_TRUNCATED on Loongson.  */
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/* { dg-do run } */
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/* loongson.h does not handle or check for MIPS16ness.  There doesn't
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   seem any good reason for it to, given that the Loongson processors
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   do not support MIPS16.  */
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/* { dg-options "isa=loongson -mhard-float -mno-mips16 -O1" } */
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/* See PR 52155.  */
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/* { dg-options "isa=loongson -mhard-float -mno-mips16 -O1 -mlong64" { mips*-*-elf* && ilp32 } } */
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#include "loongson.h"
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#include <assert.h>
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typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t;
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void
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main1 (int shift)
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{
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  int32x2_encap_t s;
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  int32x2_encap_t r;
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  s.a[0] = 0xffffffff;
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  s.a[1] = 0xffffffff;
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  /* Loongson SIMD use low-order 7 bits to specify the shift amount.
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     Thus V2SI << 0x40 == 0.  The below expression 'shift & 0x3f' will be
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     mis-optimized as 'shift', if SHIFT_COUNT_TRUNCATED is nonzero.  */
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  r.v = psllw_s (s.v, (shift & 0x3f));
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  assert (r.a[0] == 0xffffffff);
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  assert (r.a[1] == 0xffffffff);
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}
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int
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main (void)
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{
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  main1 (0x40);
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  return 0;
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}

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