OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [mips/] [mult-9.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-options "-O2 -mgp64 (-mips16)" } */
2
/* { dg-final { scan-assembler "\tmultu\t" } } */
3
/* { dg-final { scan-assembler "\tmflo\t" } } */
4
/* { dg-final { scan-assembler "\tmfhi\t" } } */
5
/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */
6
/* { dg-final { scan-assembler "\tdsrl\t" } } */
7
 
8
typedef unsigned int DI __attribute__((mode(DI)));
9
typedef unsigned int SI __attribute__((mode(SI)));
10
 
11
MIPS16 DI
12
f (SI x, SI y)
13
{
14
  return (DI) x * y;
15
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.