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[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [mips/] [r10k-cache-barrier-1.c] - Blame information for rev 696

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Line No. Rev Author Line
1 691 jeremybenn
/* { dg-options "-O2 -mabi=64 -mr10k-cache-barrier=store" } */
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/* Test that stores to uncached addresses do not get unnecessary
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   cache barriers.  */
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#define TEST(ADDR)                                      \
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  NOMIPS16 void                                         \
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  test_##ADDR (int n)                                   \
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  {                                                     \
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    while (n--)                                         \
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      {                                                 \
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        *(volatile char *) (0x##ADDR##UL) = 1;          \
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        *(volatile short *) (0x##ADDR##UL + 2) = 2;     \
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        *(volatile int *) (0x##ADDR##UL + 4) = 0;       \
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      }                                                 \
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  }
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TEST (9000000000000000)
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TEST (900000fffffffff8)
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TEST (9200000000000000)
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TEST (920000fffffffff8)
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TEST (9400000000000000)
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TEST (940000fffffffff8)
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TEST (9600000000000000)
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TEST (960000fffffffff8)
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TEST (b800000000000000)
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TEST (b80000fffffffff8)
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TEST (ba00000000000000)
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TEST (ba0000fffffffff8)
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TEST (bc00000000000000)
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TEST (bc0000fffffffff8)
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TEST (be00000000000000)
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TEST (be0000fffffffff8)
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TEST (ffffffffa0000000)
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TEST (ffffffffbffffff8)
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/* { dg-final { scan-assembler-not "\tcache\t" } } */

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