OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [mips/] [sdata-4.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-options "-G4 -mexplicit-relocs -mno-gpopt" } */
2
 
3
/* { dg-final { scan-assembler-not "%gp_?rel" } } */
4
/* { dg-final { scan-assembler-not "\\\$gp" } } */
5
 
6
static int l4a;
7
static int l4b = 1;
8
static int __attribute__((section(".sdata"))) l4c;
9
extern int e4a;
10
extern int __attribute__((section(".sdata"))) e4b;
11
int __attribute__((common)) c4;
12
int __attribute__((nocommon)) g4a;
13
int g4b = 1;
14
int __attribute__((section(".sdata"))) g4c = 2;
15
 
16
static int l8a[2];
17
static int l8b[2] = { 1, 2 };
18
static int __attribute__((section(".sdata"))) l8c[2];
19
extern int e8a[2];
20
extern int __attribute__((section(".sdata"))) e8b[2];
21
int __attribute__((common)) c8[2];
22
int __attribute__((nocommon)) g8a[2];
23
int g8b[2] = { 1, 2 };
24
int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
25
 
26
int f32a (void) { return l4a; }
27
int f32b (void) { return l4b; }
28
int f32c (void) { return l4c; }
29
int f32d (void) { return e4a; }
30
int f32e (void) { return e4b; }
31
int f32f (void) { return c4; }
32
int f32g (void) { return g4a; }
33
int f32h (void) { return g4b; }
34
int f32i (void) { return g4c; }
35
 
36
int f64a (void) { return l8a[0]; }
37
int f64b (void) { return l8b[0]; }
38
int f64c (void) { return l8c[0]; }
39
int f64d (void) { return e8a[0]; }
40
int f64e (void) { return e8b[0]; }
41
int f64f (void) { return c8[0]; }
42
int f64g (void) { return g8a[0]; }
43
int f64h (void) { return g8b[0]; }
44
int f64i (void) { return g8c[0]; }

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.