URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [mips/] [stack-1.c] - Blame information for rev 724

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* { dg-options "-O2" } */`
2			`/* { dg-final { scan-assembler "addiu\t(\\\$sp,)?\\\$sp,\[1-9\]" } } */`
3			`/* { dg-final { scan-assembler "\tlw\t" } } */`
4			`/* { dg-final { scan-assembler-not "addiu\t(\\\$sp,)?\\\$sp,\[1-9\].\tlw\t" } } /`
5
6			`int foo (int y)`
7			`{`
8			`volatile int a = y;`
9			`volatile int *volatile b = &a;`
10			`return *b;`
11			`}`