URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [440-macchw-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log


/* Test generation of macchw on 440.  */
/* Origin: Joseph Myers <joseph@codesourcery.com> */
/* { dg-do compile } */
/* { dg-require-effective-target ilp32 } */
/* { dg-options "-O2 -mcpu=440" } */
 
/* { dg-final { scan-assembler "macchw " } } */
 
int
f(int a, int b, int c)
{
  a += (short)b * (c >> 16);
  return a;
}

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* Test generation of macchw on 440. */`
2			`/* Origin: Joseph Myers <joseph@codesourcery.com> */`
3			`/* { dg-do compile } */`
4			`/* { dg-require-effective-target ilp32 } */`
5			`/* { dg-options "-O2 -mcpu=440" } */`
6
7			`/* { dg-final { scan-assembler "macchw " } } */`
8
9			`int`
10			`f(int a, int b, int c)`
11			`{`
12			`a += (short)b * (c >> 16);`
13			`return a;`
14			`}`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [440-macchw-1.c] - Blame information for rev 691