OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-19.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile { target powerpc*-*-* } } */
2
/* { dg-require-effective-target powerpc_altivec_ok } */
3
/* { dg-options "-maltivec" } */
4
/* { dg-final { scan-assembler "dst" } } */
5
 
6
void foo ( char* image )
7
{
8
  while ( 1 )
9
    {
10
      __builtin_altivec_dst( (void *)( (long)image & ~0x0f ), 0, 0 );
11
      image += 48;
12
    }
13
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.