OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-31.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile { target powerpc*-*-* } } */
2
/* { dg-require-effective-target powerpc_altivec_ok } */
3
/* { dg-options "-maltivec" } */
4
 
5
#define f0(type) void x0##type (vector _Bool type x) { }
6
f0 (int)
7
 
8
#define f1(v, type) void x1##type (v _Bool type x) { }
9
f1 (vector, int)
10
 
11
#define f2(b, type) void x2##type (vector b type x) { }
12
f2 (_Bool, int)
13
 
14
#define f3(v, b, type) void x3##type (v b type x) { }
15
f3 (vector, _Bool, int)
16
 
17
#define f4(v, b, type) void x4##type (v type b x) { }
18
f4 (vector, _Bool, int)
19
 
20
#define B _Bool
21
#define I int
22
#define BI _Bool int
23
#define VBI vector _Bool int
24
 
25
vector _Bool int a;
26
vector B int b;
27
vector B I c;
28
vector BI d;
29
VBI e;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.