OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-perm-1.c] - Blame information for rev 715

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-require-effective-target powerpc_altivec_ok } */
3
/* { dg-options "-O -maltivec -mno-vsx" } */
4
 
5
typedef unsigned char V __attribute__((vector_size(16)));
6
 
7
V b1(V x)
8
{
9
  return __builtin_shuffle(x, (V){ 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, });
10
}
11
 
12
V b2(V x)
13
{
14
  return __builtin_shuffle(x, (V){ 2,3,2,3, 2,3,2,3, 2,3,2,3, 2,3,2,3, });
15
}
16
 
17
V b4(V x)
18
{
19
  return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, });
20
}
21
 
22
V p2(V x, V y)
23
{
24
  return __builtin_shuffle(x, y,
25
        (V){ 1,  3,  5,  7,  9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });
26
 
27
}
28
 
29
V p4(V x, V y)
30
{
31
  return __builtin_shuffle(x, y,
32
        (V){ 2,  3,  6,  7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });
33
}
34
 
35
V h1(V x, V y)
36
{
37
  return __builtin_shuffle(x, y,
38
        (V){ 0, 16,  1, 17,  2, 18,  3, 19,  4, 20,  5, 21,  6, 22,  7, 23 });
39
}
40
 
41
V h2(V x, V y)
42
{
43
  return __builtin_shuffle(x, y,
44
        (V){ 0,  1, 16, 17,  2,  3, 18, 19,  4,  5, 20, 21,  6,  7, 22, 23 });
45
}
46
 
47
V h4(V x, V y)
48
{
49
  return __builtin_shuffle(x, y,
50
        (V){ 0,  1,  2,  3, 16, 17, 18, 19,  4,  5,  6,  7, 20, 21, 22, 23 });
51
}
52
 
53
V l1(V x, V y)
54
{
55
  return __builtin_shuffle(x, y,
56
        (V){ 8, 24,  9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 });
57
}
58
 
59
V l2(V x, V y)
60
{
61
  return __builtin_shuffle(x, y,
62
        (V){ 8,  9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 });
63
}
64
 
65
V l4(V x, V y)
66
{
67
  return __builtin_shuffle(x, y,
68
        (V){ 8,  9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 });
69
}
70
 
71
/* { dg-final { scan-assembler-not "vperm" } } */
72
/* { dg-final { scan-assembler "vspltb" } } */
73
/* { dg-final { scan-assembler "vsplth" } } */
74
/* { dg-final { scan-assembler "vspltw" } } */
75
/* { dg-final { scan-assembler "vpkuhum" } } */
76
/* { dg-final { scan-assembler "vpkuwum" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.