OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [gcse-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile { target { *-*-linux* && ilp32 } } } */
2
/* { dg-options "-O2" } */
3
/* { dg-final { scan-assembler-times "@ha" 1 } } */
4
 
5
 
6
/* Test for PR 7003, address of array loaded int register
7
   twice without any need. */
8
 
9
extern const char flags [256];
10
 
11
unsigned char * f (unsigned char * s) {
12
  while (flags[*++s]);
13
  while (!flags[*++s]);
14
  return s;
15
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.