OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [pr27158.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile { target powerpc*-*-* } } */
2
/* { dg-require-effective-target powerpc_altivec_ok } */
3
/* { dg-options "-O2 -maltivec" } */
4
#define REGLIST                                                              \
5
         "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",\
6
         "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",\
7
         "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",\
8
        "107", "108"
9
 
10
typedef __attribute__ ((vector_size (16))) float v4sf;
11
 
12
void
13
foo (int H)
14
{
15
  volatile v4sf tmp;
16
  while (H-- > 0)
17
    {
18
      asm ("" : : : REGLIST);
19
      tmp = (v4sf) __builtin_altivec_vspltisw (1);
20
    }
21
}
22
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.