OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [s390/] [20030129-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* This used to ICE due to a reload bug on s390*.  */
2
 
3
/* { dg-do compile } */
4
/* { dg-options "-O2" } */
5
 
6
int f (unsigned int);
7
void g (void *);
8
 
9
void test (void *p, void *dummy)
10
{
11
  unsigned int flags = 0;
12
 
13
  if (dummy)
14
    g (dummy);
15
 
16
  if (p)
17
    flags |= 0x80000000;
18
 
19
  asm volatile ("" : : : "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12");
20
 
21
  if (dummy)
22
    g (dummy);
23
 
24
  if (p)
25
    {
26
      flags |= 0x20000000|0x80000000;
27
 
28
      if (!f (0))
29
        flags &= ~0x80000000;
30
    }
31
 
32
  f (flags);
33
 
34
  if (dummy)
35
    g (dummy);
36
}
37
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.