OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [s390/] [20040305-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
 
2
/* The testcase failed due to corrupted alias information.
3
   During the crossjump analyzing step the mem alias info of the
4
   st instructions are merged and get copied during basic block
5
   reordering which leads to an insn with wrong alias info.
6
   The scheduler afterwards exchanges the mvc and st instructions
7
   not recognizing the anti dependence.  */
8
/* { dg-do run } */
9
/* { dg-options "-O3 -mtune=z990 -fno-inline" } */
10
 
11
extern void exit (int);
12
extern void abort (void);
13
 
14
int f;
15
int g;
16
int h;
17
 
18
int* x  = &f;
19
int* p1 = &g;
20
int* p2 = &h;
21
 
22
int
23
foo(void)
24
{
25
 
26
  if (*x == 0)
27
    {
28
      x = p1;         /* mvc - memory to memory */
29
      p1 = (int*)0;   /* st  - register to memory */
30
      return 1;
31
    }
32
  if (*x == 5)
33
    {
34
      f = 1;
35
      g = 2;
36
 
37
      p2 = (int*)0;   /* st */
38
      return 1;
39
    }
40
}
41
 
42
int
43
main (int argc, char** argv)
44
{
45
  foo ();
46
 
47
  /* If the scheduler has exchanged the mvc and st instructions,
48
     x is 0. The expected result is &g.  */
49
  if (x == &g)
50
    exit (0);
51
  else
52
    abort ();
53
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.