URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [s390/] [pr36822.c] - Blame information for rev 801

Go to most recent revision | Details | Compare with Previous | View Log


/* This used to ICE on s390 due to bug in the definition of the 'R'
   constraint which replaced the 'm' constraint (together with 'T')
   while adding z10 support.  */
 
/* { dg-do compile } */
/* { dg-options "-O" } */
 
int boo()
{
  struct {
    unsigned char pad[4096];
    unsigned long bar;
  } *foo;
  asm volatile( "" : "=m" (*(unsigned long long*)(foo->bar))
                : "a" (&foo->bar));
}

Line No.	Rev	Author	Line
1	691	jeremybenn	`/* This used to ICE on s390 due to bug in the definition of the 'R'`
2			`constraint which replaced the 'm' constraint (together with 'T')`
3			`while adding z10 support. */`
4
5			`/* { dg-do compile } */`
6			`/* { dg-options "-O" } */`
7
8			`int boo()`
9			`{`
10			`struct {`
11			`unsigned char pad[4096];`
12			`unsigned long bar;`
13			`} *foo;`
14			`asm volatile( "" : "=m" ((unsigned long long)(foo->bar))`
15			`: "a" (&foo->bar));`
16			`}`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [s390/] [pr36822.c] - Blame information for rev 801