OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [bmaskbshuf.c] - Blame information for rev 704

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O -mcpu=ultrasparc3 -mvis -mvis2" } */
3
typedef long long int64_t;
4
typedef int vec32 __attribute__((vector_size(8)));
5
typedef short vec16 __attribute__((vector_size(8)));
6
typedef unsigned char vec8 __attribute__((vector_size(8)));
7
 
8
long test_bmask (long x, long y)
9
{
10
  return __builtin_vis_bmask (x, y);
11
}
12
 
13
vec16 test_bshufv4hi (vec16 x, vec16 y)
14
{
15
  return __builtin_vis_bshufflev4hi (x, y);
16
}
17
 
18
vec32 test_bshufv2si (vec32 x, vec32 y)
19
{
20
  return __builtin_vis_bshufflev2si (x, y);
21
}
22
 
23
vec8 test_bshufv8qi (vec8 x, vec8 y)
24
{
25
  return __builtin_vis_bshufflev8qi (x, y);
26
}
27
 
28
int64_t test_bshufdi (int64_t x, int64_t y)
29
{
30
  return __builtin_vis_bshuffledi (x, y);
31
}
32
 
33
/* { dg-final { scan-assembler "bmask\t%" } } */
34
/* { dg-final { scan-assembler "bshuffle\t%" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.