OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [combined-1.c] - Blame information for rev 753

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn 
/* { dg-do compile } */
2 
/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
3 
typedef short vec16 __attribute__((vector_size(8)));
4 
typedef int vec32 __attribute__((vector_size(8)));
5 
 
6 
vec16 fun16(vec16 a, vec16 b)
7 
{
8 
  return (~a & b) + (b | a) - (a ^ b);
9 
}
10 
 
11 
vec32 fun32(vec32 a, vec32 b)
12 
{
13 
  return (~a & b) + (b | a) - (a ^ b);
14 
}
15 
 
16 
/* This should be transformed into ~b & a.  */
17 
vec16 fun16b(vec16 a, vec16 b)
18 
{
19 
  return (a & ~b) + (b | a) - (a ^ b);
20 
}
21 
 
22 
vec32 fun32b(vec32 a, vec32 b)
23 
{
24 
  return (a & ~b) + (b | a) - (a ^ b);
25 
}
26 
 
27 
/* { dg-final { scan-assembler-times "fandnot1\t%" 4 } } */
28 
/* { dg-final { scan-assembler-times "for\t%" 4 } } */
29 
/* { dg-final { scan-assembler-times "fpadd" 4 } } */
30 
/* { dg-final { scan-assembler-times "fxor\t%" 4 } } */
31 
/* { dg-final { scan-assembler-times "fpsub" 4 } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.