OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [edgen.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn 
/* { dg-do compile } */
2 
/* { dg-options "-O -mcpu=ultrasparc3 -mvis" } */
3 
 
4 
long test_edge8n (void *p1, void *p2)
5 
{
6 
  return __builtin_vis_edge8n (p1, p2);
7 
}
8 
 
9 
long test_edge8ln (void *p1, void *p2)
10 
{
11 
  return __builtin_vis_edge8ln (p1, p2);
12 
}
13 
 
14 
long test_edge16n (void *p1, void *p2)
15 
{
16 
  return __builtin_vis_edge16n (p1, p2);
17 
}
18 
 
19 
long test_edge16ln (void *p1, void *p2)
20 
{
21 
  return __builtin_vis_edge16ln (p1, p2);
22 
}
23 
 
24 
long test_edge32n (void *p1, void *p2)
25 
{
26 
  return __builtin_vis_edge32n (p1, p2);
27 
}
28 
 
29 
long test_edge32ln (void *p1, void *p2)
30 
{
31 
  return __builtin_vis_edge32ln (p1, p2);
32 
}
33 
 
34 
/* { dg-final { scan-assembler "edge8n\t%" } } */
35 
/* { dg-final { scan-assembler "edge8ln\t%" } } */
36 
/* { dg-final { scan-assembler "edge16n\t%" } } */
37 
/* { dg-final { scan-assembler "edge16ln\t%" } } */
38 
/* { dg-final { scan-assembler "edge32n\t%" } } */
39 
/* { dg-final { scan-assembler "edge32ln\t%" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.