OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [setcc-1.c] - Blame information for rev 691

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 691 jeremybenn
/* { dg-do compile } */
2
/* { dg-options "-O1" } */
3
 
4
int neq (int a, int b)
5
{
6
  return a != b;
7
}
8
 
9
int eq (int a, int b)
10
{
11
  return a == b;
12
}
13
 
14
int lt (unsigned int a, unsigned int b)
15
{
16
  return a < b;
17
}
18
 
19
int leq (unsigned int a, unsigned int b)
20
{
21
  return a <= b;
22
}
23
 
24
int geq (unsigned int a, unsigned int b)
25
{
26
  return a >= b;
27
}
28
 
29
int gt (unsigned int a, unsigned int b)
30
{
31
  return a > b;
32
}
33
 
34
/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
35
/* { dg-final { scan-assembler-times "subcc\t%" 2 } } */
36
/* { dg-final { scan-assembler-times "addx\t%" 3 } } */
37
/* { dg-final { scan-assembler-times "subx\t%" 3 } } */
38
/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */
39
/* { dg-final { scan-assembler-not "sra\t%" { target lp64 } } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.